GROUNDED: Your PCB, EMC/EMI, and SI Nuggets

Today, I reviewed EMI issues on a 6-layer board based on the AllWinner-A64 processor, and spotted a couple of design flaws worth sharing.

The first issue was a poorly chosen stackup:

🔹 L1: Signal

🔹 L2: Ground (Return Reference Plane)

🔹 L3: Signal

🔹 L4: Signal

🔹 L5: Power

🔹 L6: Signal

Right away, it’s clear this stackup doesn’t properly manage signal energy or field control—especially with Layer 5 (L5).

L5, which carries multiple power rails, was segmented into different polygons to supply power to various components.

This choice disrupts the signal layers (L4 and L6), which rely on L5 as their reference plane.

In a PCB, signal traces on one layer (like L4 or L6) form a transmission line with their reference plane (L5 here), guiding the signal’s electromagnetic fields along the path.

But when L5 is split into separate power polygons, gaps form between them.

As a signal crosses these gaps, it loses its continuous reference plane, letting the fields spread uncontrollably.

One major result is crosstalk—when a signal’s energy interferes with nearby traces.

This noise can couple to other transmission lines, causing internal signal integrity issues.

Worse, if it reaches structures like cables connected to the board, those cables can act as antennas, radiating electromagnetic interference (EMI).

Proper filtering in the right spots "might" suppress this noise onboard, but without it, EMI becomes a serious risk.

When EMI escapes, EMC test equipment detects this excess energy, leading to a failed test.

TLDR: Ensure signal traces have a solid, uninterrupted reference plane for their entire path to prevent field expansion, crosstalk, and EMI.

A segmented power plane like this is a recipe for trouble.

-Dario

P.S. Want to master EMC/EMI in PCB Design?

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