This is one of the reasons why many hardware designers fail to pass EMC tests.
This is also one of the hardest concepts I struggled with when I started with PCB design.
But I promise you that once you integrate it, your designs will be halfway to passing EMC tests.
I say halfway because the other missing part of this picture is understanding the importance of the current loop and return current. But we'll leave that for another day.
What you see in this picture is the representation of a signal propagating in the PCB.
This is when the digital signal (in red) is propagating from the source towards the load as an electromagnetic wave between the conductors, which are only guiding the wave.
The thing that I struggled to understand was the fact that the signal is established between the two conductors, in this case, the signal trace and the return reference plane.
This is important because it also means that the energy is in the space between the two conductors.
So, why did I say that many fail EMC tests because of this?
Because clients keep showing me boards that are built without the return reference plane adjacent to the signal trace in their PCB stackup.
What's the result of doing this?
Simply that the electromagnetic (EM) fields are no longer contained.
This means that when you are measuring the EM fields during the EMC test, these fields are going to be large.
Large enough that they are no longer within the limits set by the EMC standards.
So it is not a question of whether your circuit will work or not.
Because even if it "works", which means the fields are now established through different paths, that does not mean that the fields are contained.
I wanted to show you this picture just so that when you are deciding on how to set up the stackup, you keep this in mind.
You need two conductors adjacent to each other, not just one, if you want to contain the fields between them.
This is setting the boundary conditions for the EM fields.
One is for potential A and the other one for potential B (the reference potential).
That's why when you design PCBs with 2 layers and both of them are dedicated to signals (only potential A), and none is dedicated to the return current and the reference potential (potential B), you are most likely to fail EMC tests and generate EMI.
I explain this more in-depth in my video lessons.
For now, I hope this helps get a portion of the picture.
Dario
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