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PCB Design Review For Low EMI: Motherboard Design



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In this article, I will guide you through the basics of conducting an EMI project review for a Printed Circuit Board layout.


The focus will be on a motherboard design featuring AllWinner-A64 processors, a relatively complex system.


The project we are going to review is the TERES-I from Olimex.


As EMI specialists, we’ll explore the critical areas to address in order to optimize the board’s EMI performance.


 

PCB Stackup


One of the first things I check during an EMI review is whether the stackup is correct.

Getting the stackup right accounts for about 90% of the EMI performance.


Why is that?


Because the stackup determines how the electromagnetic fields are contained within the PCB.


What do I mean by that?


In PCB design, layers always come in pairs.


For example, if I have a signal layer, there must automatically be a return reference plane (RRP) adjacent to it—this should be second nature.


What does "adjacent" mean?

It means the return reference plane should be directly above or below the signal layer.


Comparison between 2 layers PCB stackup
Figure 1 - Comparison between 2 layers PCB stackup

It’s important that the return reference plane (RRP) is placed as close as possible to the signal layer to do its job effectively.


As the name suggests, the RRP provides the return path for the current to flow back to its source, and it also offers a reference potential for the signal layer.


If this setup is not in place, we are likely to face EMI issues as well as signal integrity problems. This is because, without proper containment, the electromagnetic fields can "spread out" rather than being confined by the stackup.


When the RRP is placed as close as possible to the signal layer, the electromagnetic fields remain "smaller" and more controlled.


One key point to highlight is that the power layer does not work well as a return reference plane.


This is because, for the return current to flow back to its source, it would need to cross multiple layers before finally closing the loop and reaching the source pin. This leads to poor EMI performance and signal integrity.



Example of a Power plane used instead of a RRP.
Figure 2 - Example of a Power plane used instead of a RRP.

What does this mean?


It means that the return current must travel through the space between the layers, which has its own impedance. As the current flows through this space, it creates a voltage drop that introduces noise within the stackup.


This noise can lead to crosstalk between signals on adjacent layers and may even cause emissions from the edges of the board.


For this reason, I do not recommend using the power plane as a return path, especially for high-speed signals.


You might have heard suggestions about using stitching capacitors, but the issue is that the impedance of these capacitors at high frequencies tends to be inductive.

Example of the capacitor Impedance
Figure 3 - Example of the capacitor Impedance

This means that the high-frequency portion of the return current will not flow through the decoupling capacitor; instead, it will travel through the layers as displacement current.


As a result, this displacement current will spread between the layers, seeking the path of least impedance to return to the source and complete the current loop.


In contrast, the low-frequency portion of the current flowing through the decoupling capacitor often takes a larger loop, which can create common mode currents that lead to emissions.


For these reasons, we should avoid using the power layer as a return layer.

At least, I no longer do!


 

Optimal 6 Layers Stackup


We can immediately see that the stackup is composed of 6 layers.


PCB stackup of the board.
Figure 4 - PCB Stackup of the board.

I expect to see at least two Return Reference Planes (RRP) because each signal should have an RRP adjacent to it, or at least on one side where it couples.


There are several ways this stackup can work effectively, particularly in terms of EMI and signal integrity.


Stackup Option 1


One option is to have Layer 1 dedicated to signals and power, paired with the RRP on Layer 2. Layer 3 can also have signals and power, paired with the RRP on Layer 2. The remaining layers, Layers 4, 5, and 6, would mirror the first three layers.


This configuration means Layer 4 will have signals and power paired with Layer 5 as the full RRP, and Layer 6 will also be paired with the RRP on Layer 5.


We can achieve this due to the skin depth effect, which allows return currents from Layers 1 and 3 to reside on Layer 2 without mixing. The return current from Layer 1 occupies one side of Layer 2, while the return current from Layer 3 occupies the opposite side.


Skin depth effect in the PCB stackup.
Figure 5 - Skin depth effect in the PCB stackup.

This arrangement ensures that the skin depth calculated for the signals permits two different return currents without causing crosstalk.


The same principle applies to Layer 5, which serves as the RRP for both Layers 4 and 6.


When I refer to signals and power, I mean routed with tracks rather than as planes or large copper pours.


With this stackup, we effectively utilize four layers for signals and power, potentially creating a more cost-effective design. However, we must be cautious that Layers 3 and 4 do not interfere with each other, making a thicker dielectric layer between them advisable.


Stackup Option 2


Another effective stackup option is to pair Layer 1 as signals with Layer 2 as the RRP. Similarly, Layer 6 can serve as signals paired with Layer 5 as the RRP.


In this setup, Layers 3 and 4 can be dedicated power planes, increasing the amount of current we can deliver.


Stackup Option 3 - Mixed


A mixed option combines the two approaches I just proposed. In this setup, Layers 1 and 6 are used for signals and power, while Layers 2 and 5 serve as RRPs. Layers 3 and 4 can be used interchangeably as signals or power planes.


They do not need to be of the same type; for example, Layer 3 can be a signal layer while Layer 4 can be a power plane.


These configurations represent some of the most effective combinations for a six-layer stackup.


As a general rule, always think in terms of assigning layers in pairs, not as individual layers. Each pair should consist of signals and RRPs or power and RRPs.


In any case, an RRP must be present. Any deviation from this structure can create antenna-like behaviors and result in poor EMI performance, as the electromagnetic fields will begin to spread.


 

Analysis of the Current Board Stackup


Now, we will examine the layer arrangement and conduct an analysis to ensure that the stackup does not introduce potential EMI issues.

The first layer is dedicated to components and signal routing, along with some power distribution.


Layer 1
Figure 6 - Layer 1


This is a typical choice.

As mentioned earlier, the second layer should serve as the Return Reference Plane (RRP).

Let's take a look at what has been implemented here.



Layer 2
Figure 7 - Layer 2

Great! This aligns perfectly with our expectations.


With this configuration, we have a complete pair for Layers 1 and 2.


Notice how the second layer is a solid plane without splits, cuts, or large gaps. This ensures that the signals on Layer 1 always have an RRP directly underneath throughout their entire propagation.


By examining any trace on the board and verifying that there’s a good RRP beneath it, you can avoid impedance discontinuities. This is crucial for maintaining a consistent signal and preventing issues like reflections or unwanted emissions that can occur when impedance changes.


Now, let’s take a look at Layer 3.



Layer 3
Figure 8 - Layer 3

This layer is also a plane, but this time it includes some digital signals. This is still a good configuration, as the signals on Layer 3 are paired with the RRP on Layer 2.


Now, let’s examine Layer 4.


Layer 4
Figure 9 - Layer 4

This is where most of the routing has been done, featuring many digital and power signals. Additionally, there are large sections of copper connected to the ground (GND) net.


So far, so good.


As I mentioned earlier, I expect Layer 5 to serve as another RRP, which should pair with the signals on Layer 4.


Let’s see what has been chosen for this layer.


Layer 5
Figure 10 - Layer 5

Here, we have a mixed power layer.

There is a large copper area for the 3.3V supply, along with other voltages represented by traces or polygon fills.

This configuration may lead to issues for us.


Now, let’s examine the last layer, Layer 6.

Layer 6
Figure 11 - Layer 6

This layer is dedicated to digital signals and power, and it includes a large copper area for the ground (GND) net.


Now, let me explain the issues with having the power layer on Layer 5.


There are two main problems that arise from this configuration, which makes this plane unsuitable for providing the return path for the currents from Layers 4 and 6:


  1. Impedance Discontinuity: First, we have signals crossing splits horizontally. This results in parts of the signals lacking a plane beneath them, leading to impedance discontinuity. This means that when the signal reaches the split, its impedance changes, resulting in signal variations and reflections.


  1. Return Current Path: The return current from Layers 4 and 6 now flows in Layer 5, but it still needs to return to the source to close the current loop. Since Layer 5 is not connected to Layer 2 (the reference plane and zero-volt potential for the signal), the return current must find a way to travel from Layer 5 to Layer 2. However, there is no DC connection between the two layers. Remember, Layer 2 is the GND net, while Layer 5 is a power layer. If there were a DC connection between them, it would create a short circuit! Thus, the return current relies on capacitance between these two planes.


This connection occurs either through decoupling capacitors between Layer 5 and Layer 2 or through the internal capacitance between the layers, which means the return current travels as displacement current. As mentioned earlier, the challenge with conduction current flowing through the capacitors is that their impedance remains low only up to the resonant frequency. Beyond this frequency, the capacitor’s impedance becomes increasingly inductive.


The low-frequency portion of the current flowing through these capacitors will create larger current loops, which can generate common mode voltage sources, a significant concern for emissions.


The high-frequency component of the current that must return to the source, traveling as displacement current, must flow through the dielectric between the layers. This causes it to spread in search of the path of least impedance to reach the source.


As it crosses the dielectric, this material also possesses impedance; otherwise, we wouldn't observe any current flow.


As the current flows through this impedance, it generates a voltage drop across the layers. This voltage drop manifests as noise between the layers, which can also lead to emissions from the edges of the board.


Consequently, this can result in EMI issues and signal integrity problems, as this noise couples with other signals transitioning from one layer to another via vias.


This is why, as mentioned previously, we avoid using the power plane to provide the return current for signals. The only acceptable pairs are SGN-RRP and PWR-RRP, where RRP is the reference plane.


I wouldn't recommend any other combinations unless we intentionally want to create radiators! Therefore, the stackup should be changed to one of the versions I previously described in order to maintain a 6-layer board.


However, this modification would require changing the entire layout of the board. At this point, we can discuss with the client what actions can be taken and which options are available based on the project timeline. This highlights the importance of understanding the impact of EMI before we even start laying out the board.


Another option is to introduce additional return reference planes to meet the requirements of the signals and power layers. However, this would mean increasing the stackup by at least two more layers, resulting in an 8-layer board.


In summary, we have two options:


Option 1: Keep the 6-layer configuration but re-route the board to ensure that Layer 5 serves as a Return Reference Plane.


Option 2: Add two more layers, ideally with two more return reference planes, resulting in an 8-layer board.


Option 1 is the more time-consuming choice, as it requires a layout rework, which entails additional engineering costs. However, if executed correctly, this option allows us to maintain a 6-layer board with the expected production costs.


Option 2 is faster because it likely requires only minor modifications to the layout at this stage while still ensuring a solid stackup from an EMI perspective. However, this option may increase the cost of the stackup, so we need to account for this during production.


In this case, we can place an RRP between Layers 5 and 6 to provide a return path for both. I would also position another RRP between Layers 5 and 4, ensuring a close RRP for Layer 4, which primarily carries digital signals.


Our task will be to present this information to our clients or project stakeholders, especially if we are working for a company.


 

Layout Analysis


Now that we have reviewed the stackup, let's take a look at the layout itself.


At this point, we want to ensure that there are no visible issues or anomalies in the layout.


 

By the way, if you're interested in becoming an EMI specialist yourself, visit our website at fresuelectronics.com/mentoring


There, you’ll find details on how to apply for one of our exclusive programs designed to help you achieve that goal.

 

Antenna-like Structures

The first thing we are going to check is for antenna-like structures.


I can already see something I'm not particularly fond of: the way some copper pours have been used.



Example of an antenna-like structure
Figure 12 - Example of an antenna-like structure

This is concerning because these structures can create emissions problems.


What do I mean by antenna-like structures?


For example:


  • Floating Copper Islands: If there are copper areas that are not properly connected or not connected at all, they can act as small antennas. These floating patches can pick up or radiate signals, leading to EMI. Even if they are connected but not sufficiently, these portions of copper fills will still behave like antenna structures. Depending on the frequency of the signals that couple to them, voltage drops can occur through the parasitics of the copper fill, causing them to radiate.


  • Long, Thin Traces with No Return Path: When these traces extend over long distances without a nearby return reference plane, they can behave like dipole antennas, radiating energy into the environment.


  • Unconnected Stubs or Branches: Sometimes, designers leave unused portions of copper or traces branching off signal lines. These stubs can reflect signals and radiate them, acting like antennas.


  • Presence of Slots or Gaps in the Return Reference Plane: We've covered this during the stackup analysis, so we won’t elaborate further. We will ensure this issue is resolved by selecting the appropriate stackup proposed earlier.